Effect of high-temperature on holding characteristics in MOSFET ESD protecting device

Abstract

The holding voltage of electrostatic discharge (ESD) protecting structure is the critical parameter to determine the latch-up performance of the protecting device, but the thermal change of ESD device parameters lead the protecting device to suffer latch-up risk at high ambient temperature. In this paper, the holding characteristics of the ESD protecting device at various ambient temperatures ranging from 30 ℃ to 195 ℃ are studied. The investigated ESD structure is the N-channel metal oxide semiconductor (NMOS) transistors fabricated with the 0.18 μm partially depleted silicon-on-insulator process. The ESD characteristics of the device are measured by the transmission line pulse test system at different ambient temperatures. The test results show that the holding voltage (<i>V</i>_H) decreases with temperature increasing. The TCAD simulation is carried out to support and analyze the experimental results, and the same trend of <i>V</i>_H versus temperature is obtained. Through the analysis of simulation results and theoretical derivation, the underlying physical mechanisms related to the effects of temperature on <i>V</i>_H and holding current (<i>I</i>_H) are discussed in detail. When the drain is subjected to the same current pulsing and the Source and Body are both grounded, the distributions of current density, electric potential, and injected electron density of NMOS at various temperatures are extracted and analyzed. When the Drain, Source, and Body are all grounded, the distributions of the electrostatic field at various temperatures are extracted and analyzed. The distribution of electric potential in NMOS indicates that the voltage drop on the Drain-Body junction (<i>V</i>_DB) is affected by ambient temperature significantly, and the variation of <i>V</i>_DB dominates the variation trend of <i>V</i>_H with temperature increasing. The reducing electrostatic field and increasing injected electron density with temperature decreasing contribute to the decreasing of <i>V</i>_DB. The trend of <i>I</i>_H and parasitic Body resistance (<i>R</i>_Body) weakens the temperature dependence of the <i>V</i>_H. The current gain of parasitic bipolar transistor (<i>β</i>) decreases with ambient temperature rising, which is the main contributor to the decreasing of <i>I</i>_H. Therefore, increasing <i>I</i>_H and <i>R</i>_Body is helpful in reducing the temperature dependence of the latch-immune ESD protection structure.