Analysis of the back-gate effect on the breakdown behavior of lateral high-voltage SOI transistors

Abstract

A novel back-gate reduced bulk field concept which makes a breakthrough in improving the vertical breakdown voltage of high voltage SOI transistors is proposed. The mechanism of the improved breakdown characteristics is that the electric field distributions of the active region are modulated by the interface charges induced by the back-gate voltage. The bulk electric field at the drain side is reduced, the bulk electric field at the source side is increased, and the breakdown voltage of the high voltage SOI device is improved. The impact of the back-gate bias on thick film SOI LDMOS (over 600 V) is discussed via two-dimensional simulations. When the back-gate bias is 330V, the breakdown voltage of the three-zone SOI double RESURF LDMOS is 1020V, which is 47.83% greater than that of a conventional LDMOS. The novel concept presents a new method for realizing over 600 V high voltage power device and high voltage integrated circuit.