Implementation of High-Performance EEG Based Seizure Detection And Analysis On Multicore Platform
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Published:2020-03-21
Issue:
Volume:
Page:189-194
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ISSN:2394-4099
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Container-title:International Journal of Scientific Research in Science, Engineering and Technology
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language:en
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Short-container-title:IJSRSET
Author:
Nagashyam P.1, Vijay Kumar T.1
Affiliation:
1. Department of ECE, KVSRIT, Jawaharlal Nehru Technological University Anantapuramu, Kurnool, Andhra Pradesh, India
Abstract
About 50 million people worldwide su?er from epilepsy, the neurological disorder characterized by seizures. The primary tool for diagnosis of an epileptic seizure is an electroencephalography (EEG) which records the brain’s spontaneous electrical activity. This requires the placement of a minimum of 16 electrodes on the scalp with each electrode being interpreted as a channel. The classification of seizure detection and analysis techniques mainly work in two stages , where features are extracted from raw EEG data in the first stage and then the obtained features are used as input for the classification process in the second stage. Traditionally the Seizure detection algorithms were implemented using DSP Processor or FPGAs. But these single core platforms are constrained with respect to speed of operation and power consumption. There is a greater need to reduce the power consumption as well to increase the speed of EEG seizure detection system. This problem can be addressed using the Multicore Processors, which process data simultaneously. This project presents a high performance multicore platform for EEG based seizure detection and analysis. This platform performs continuous multichannel detection and analysis of seizures for epilepsy patients. The detection unit detects seizures based on feature extraction process once seizure detection is done enables the analysis circuit that process the data based Uridva Triyabhakyam based 128 point FFT and transmits energy and frequency contents of EEG data. All proposed blocks are simulated and synthesized using Xilinx ISE and coding is done in Verilog.
Publisher
Technoscience Academy
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