1. International Technology Roadmap for Semiconductors 2.0 2015 Edition (www.itrs2.net/itrs-reports.html) (2015). ITRS predicts that the device gate length should shrink to 10 nm and the contact critical dimension to 11 nm with 4-nm spacer width to limit the overall device footprint to 40 nm in the 3-nm technology node and beyond.
2. C.-H. Jan, F. Al-amoody, H.-Y. Chang, T. Chang, Y.-W. Chen, N. Dias, W. Hafez, D. Ingerly, M. Jang, E. Karl, S. K.-Y. Shi, K. Komeyli, H. Kilambi, A. Kumar, K. Byon, C.-G. Lee, J. Lee, T. Leo, P.-C. Liu, N. Nidhi, R. Olac-vaw, C. Petersburg, K. Phoa, C. Prasad, C. Quincy, R. Ramaswamy, T. Rana, L. Rockford, A. Subramaniam, C. Tsai, P. Vandervoorn, L. Yang, A. Zainuddin, P. Bai, A 14 nm SoC platform technology featuring 2nd generation tri-gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 μ;m2 SRAM cells, optimized for low power, high performance and high density SoC products. VLSI Symp. Tech. Digest, T12–T13 (2015).
3. Nanomaterials in transistors: From high-performance to thin-film applications
4. Carbon Nanotube Complementary Wrap-Gate Transistors
5. S.-J. Han, S. Oida, H. Park, J. B. Hannon, G. S. Tulevski, W. Haensch, Carbon nanotube complementary logic based on erbium contacts and self-assembled high purity solution tubes. IEDM Tech. Digest, 19.8.1–19.8.4 (2013).