Abstract
The foundry industry and academia dedicated to advancing logic transistors are encountering significant challenges in extending Moore's Law. In the industry, silicon (Si)-based transistors are currently adopting gate-all-around (GAA) structures and reducing channel thickness, even at the cost of decreased mobility, for maximizing gate controllability. To compensate for the reduced mobility, multi-channel structures are essential, making the fabrication process extremely challenging. Meanwhile, two-dimensional (2D) semiconductors are emerging as strong alternatives for the channel material in logic transistors, thanks to their ability to maintain crystallinity even when extremely thin. In the case of 2D semiconductors, introducing a dual gate structure, which has a much lower fabrication complexity, can achieve effects similar to GAA. Through this research, we have identified the fringing field originating from the common structure of elevated top contact in 2D FETs results in a high charge injection barrier. Through simulation and statistical analysis with large-area FET arrays, we confirmed that introducing a dual-gate structure in bilayer MoS2 FETs effectively compensates for the fringing field. We have confirmed that this leads to a significant boost in on-current. Remarkably, even with conventional contacts and polycrystalline materials, we observed a record-high on-current of 1.55 mA/µm. Additional circuit simulations have confirmed the potential for dual gate bilayer FETs to surpass the performance of Si GAAFETs when possessing a gate length of 5 nm, achievable only with 2D materials. Therefore, here we propose that by using 2D materials, we can focus on extreme gate length scaling and monolithic 3D integration rather than the challenging GAA process for extending Moore’s Law.