Multiple Fault Tolerant PUC Multilevel Inverter Using the Concept of Redundancy with Low Total Blocking Voltage, Device Count and High Post-Fault Efficiency for Five Switches Fault

Abstract

Abstract In this article, a fault-tolerant Packed U Cell MLI (FT-PUC-MLI) is presented, which utilizes two DC sources with nine main switches and eight redundant switches for creating 7-level across the output. The proposed topology uses phase disposition sinusoidal pulse width modulation (PD-SPWM) for the generation of gate signals. A detailed analysis of the proposed topology is done with respect to efficiency, power loss and total harmonics distortions (THD). A brief comparative analysis in terms of device count, total blocking voltage, post and pre fault efficiency, post and pre fault voltage levels is being done. The proposed topology can tolerate single-switch and multiple-switch failures, thus enabling it to be used for emergency loads. The proposed topology maintains a constant output voltage level in the post-fault period. The simulation of FT-PUC-MLI topology is carried out by using the MATLAB/SIMULINK platform with all possible switch fault combinations and real time simulation is also being done in OPAL RT 4510.