Abstract
In recent years, the demand for low-power devices has surged, driven by the scaling of CMOS technology, resulting in smaller chip sizes and higher transistor densities within System on Chip (SoC) designs, including memory components. This paper introduces the design and evaluation of Memristor-based SRAM, leveraging the unique properties of memristors to enhance power efficiency and processing speed. The integration of memristors reduces the transistor count, transitioning from traditional 6T SRAM to a 4T2M configuration and from 8T to 6T2M power usage. To further reduce power consumption, we implement the Multi-Threshold CMOS (MTCMOS) technique, known for minimizing leakage power by selectively deactivating inactive circuit domains. We perform a detailed analysis and parameterization of Memristor-based SRAM, including an MTCMOS-enhanced configuration, using the Cadence Virtuoso tool at a 90nm process technology with an operating voltage of 1.2 volts. This study addresses the pressing need for low-power memory solutions in modern electronic devices, focusing on the analysis and optimization of Memristor-based SRAM configurations.