Pareto technique optimization for 3D NOC architecture

Abstract

Abstract Network on-Chip (NoC) – the network-based communication between operational cores and intellectual property cores in a single chip – has been eliciting much interest in recent years. The major barrier to the effective design of NoCs has been high-speed data transfer and connections that are only required when necessary in massively parallel, multi-core, low-power applications. To solve these issues, a new technique called Pareto African Buffalo Optimized Mapping Weighted Directive Graph Theory (PABOMWDGT) is proposed in this study. The suggested method aims to locate efficient operational cores integrated on the device in the shortest time and demonstrate the effectiveness of 3D NoC. In this approach, a selection of IP cores from the benchmark dataset are first listed along with their connections. The mapping approach on the 3D NoC topology is optimized for the African buffalo. Random initialization of the IP cores (also known as buffalos) in the optimization technique's search space is performed. Every IP core in the population is used to estimate the various objective functions. The Pareto function is then examined using the African buffalo optimization technique of Deming Regression. A fitness metric is employed to determine the best fit. The position of the buffalos is updated and the best option is identified when one buffalo's fitness level exceeds that of the other. The process is repeated until the maximum number of iterations is reached. Then, mapping is done based on the probability. It is seen that it takes less time to develop an effective mapping of cores in the 3D NoC architecture. Experimental results show that the proposed PABOMWDGT technology is superior to state-of-art techniques with a 0.74 packet / cycle / IP block throughput, 140 clock cycle delay, and 11 ms computation time.