Implementation of lattice based Cryptograpy cyber forensic system-Reference-Cited by-同舟云学术

Implementation of lattice based Cryptograpy cyber forensic system

Published:2024-04-12 Issue: Volume: Page:
ISSN:
Container-title:
language:
Short-container-title:

Author:

Kumari Sonal¹,Anand Akshay¹,Sharma Shafalii¹,Pandey Diwakar¹

Affiliation:

1. Chandigarh University

Abstract

Abstract Lattice-based cryptography has emerged as a robust and promising framework for ensuring the security and resilience of cryptographic systems in the face of quantum computing threats. This research paper explores the recent advancements in lattice-based cryptographic techniques, delving into their mathematical foundations, practical implementations, and their significance in the contemporary landscape of information security. The paper provides an in-depth analysis of latticebased cryptographic protocols, including encryption schemes, digital signatures, and key exchange mechanisms. Emphasizing the post-quantum safety and impenetrability of latticebased cryptography, the research investigates the theoretical underpinnings of lattice problems and their computational complexity.

Publisher

Research Square Platform LLC

Reference17 articles.

1. FPGA based low power DES algorithm design and implementation using HTML technology;Thind V;International Journal of Software Engineering and Its Applications,2016

2. SSTL based power efficient implementation of DES security algorithm on 28nm FPGA;Pandey B;International Journal of Security and Its Application,2015

3. Thind, V., Pandey, B. and Hussain, D.A., 2016, August. Power analysis of energy efficient DES algorithm and implementation on 28nm FPGA. In 2016 IEEE Intl Conference on Computational Science and Engineering (CSE) and IEEE Intl Conference on Embedded and Ubiquitous Computing (EUC) and 15th Intl Symposium on Distributed Computing and Applications for Business Engineering (DCABES) (pp. 600–603). IEEE.

4. Kaur, A., Kumar, K., Sandhu, A., Kaur, A., Jain, A. and Pandey, B., 2019. Frequency scaling based low power ORIYA UNICODE READER (OUR) design ON 40nm and 28nm FPGA. International Journal of Recent Technology and Engineering (IJRTE) ISSN, pp.2277–3878.

5. Aditya, Y. and Kumar, K., 2022. Implementation of Novel Power Efficient AES Design on High Performance FPGA. NeuroQuantology, 20(10), p.5815.