Low Leakage Variation SRAM Cell with Improved Stability for IOT Applications

Abstract

Abstract The typical memory for very large scale integrated (VLSI) circuits has traditionally been static random access memory (SRAM). This is so because SRAM is a speedier technology than the ones that were previously mentioned. SRAM, however, has a high power consumption rate. Due to its importance in the memory architecture, it is crucial to lower the power consumption of SRAM cells. This literature review's major goal is to provide innovative and effective strategies for creating low power SRAM cells. This study provides several circuit topologies and methodologies to compute stability, leakage current, delay, and power, as well as novel techniques for designing SRAM cells based on eight transistors (8T). The static random access memory (SRAM) is frequently chosen over dynamic random access memory (DRAM) due to faster speed and lower power consumption. It is named static since no modification or action, i.e. refreshing, is required to maintain the data intact. The leakage current in SRAM, however, frequently rises and impairs its performance when technology nodes are scaled down. Voltage scaling, which also impacts the stability and latency of SRAM, is chosen as a solution to this problem. In this study, a separate (isolated) read port is employed to increase read stability while a negative bit-line (NBL) write aid circuit is used to improve write capability. In terms of write static noise margin (WSNM), write latency, read static noise margin (RSNM), and other metrics, the suggested design has been compared to state-of-the-art work. The following is how the paper is divided into sections: 1. Introduction. Section 2 describes related work. The suggested work is in section 3. Results and discussion are included in section 4 and section 5 Conclusions.