Impact of Interfacial Crack on Redistribution Layer of TSV based 3D Integration

Abstract

Abstract The interfacial strength of redistribution layer (RDL) and passivation layer plays a crucial role in ensuring the optimal performance and reliability of through silicon vias (TSVs), as it significantly impacts their electrical characteristics and thermal stability, especially in high-density packaging with constrained space. Therefore, it is important to identify and address the interfacial cracks in the RDL that arises due to the factors like manufacturing defects, mechanical stress, and thermal cycling. Neglecting these issues can lead to a range of problems, including reduced device performance, intermittent or complete loss of functionality, and even permanent damage. Owing to ensure their reliability and longevity, this paper introduces for the first time considers the RDL cracks under heating and cooling conditions to model an equivalent electrical circuit and demonstrates the performance in terms of thermal stress, power dissipation, power delay product (PDP), crosstalk delay and power loss. Remarkably, our analysis of interfacial cracked TSV has yielded highly positive results. Specifically, a striking improvement of 22.29% have been observed in case of crosstalk delay, as the minimum crack width of 0.18µm at heating mode approached towards the defect-free condition. A thorough validation of the analytical results reveals an excellent agreement with the EM result, for a negligible deviation of only 3.4% observed in the scattering parameter. This close correspondence between the simulated and quantitative results lends a strong support to the accuracy and reliability of the research findings. Furthermore, this analysis elucidated that the cooling mode is significantly more susceptible to PDP than heating, with a vulnerability that is 7.19% higher at a crack width of 0.18µm.