Abstract
Probabilistic computing—quantum-inspired computing that uses probabilistic bits (p-bits)—has emerged as a powerful method owing to its fast search speed and robust connectivity. Previous works used linear feedback shift registers (LFSRs) or stochastic magnetic tunnel junctions (MTJs) to implement p-bits. However, in large-scale problems, periodicity and correlation issues in LFSR p-bits and inherent variations in MTJ-based p-bits with narrow stochastic regions lead to unreliable results when seeking the appropriate solution. Therefore, we propose a fully CMOS frequency-scalable p-bit implemented with a discrete-time flipped-hook tent-map chaotic oscillator. The proposed chaotic oscillator produces high-quality noise voltage that is uniformly distributed across the entire supply voltage range, enabling aligned responses of p-bits free from calibration and an input resolution of 8 bits. In contrast to LFSR-based p-bits with hardware-dependent correlation, the chaotic oscillator p-bits could factorize semiprimes with lengths up to 64 bits without changing hardware size. The chaotic oscillator exhibited an energy efficiency of 4.26 pJ/bit at 1.8 V supply voltage. The robustness and the high randomness of the proposed chaotic oscillator p-bit suggest a new direction of a p-bit scalable to large-scale probabilistic computing.