High Performance and Area Efficient Multi-Operand Binary Tree Adder

Abstract

Abstract The building blocks of many digital systems like digital signal processors, microprocessors are the arithmetic units. Adders are the most important component in arithmetic processing unit. In recent times the multi operand adder (MOA) are used widely in signal and image processing applications because of its low power consumption, and it also reduces the partial sum and propagated carries. In this work multi operand binary tree adder is designed using EXOR-MUX based full adder. The proposed BTA gives an enhanced performance than the existing adder architecture which is designed based on AOI/OAI logic. The existing system takes more logic size because the OAI logic is implemented as the inverse of AOI logic. The functionality of the binary tree adder is verified using VERILOG HDL and synthesized using MODEL SIM 6.5 and XILINX ISE 14.7. The performance of the proposed binary tree adder is increased 44% with respect to area and 32% with respect to delay. Taking everything into account, the proposed BTAs outdo the existing BTAs.