BLCD: A Balanced and Low-Power Cell Design Family for Secure Applications

Abstract

Providing a secure hardware infrastructure is the main issue to implement secure cryptographic algorithms. Just a robust algorithm with suitable key lengths is not effective against differential analysis attacks and can cause the cryptographic key to be discovered. Today, credit cards and electronic identification cards, due to the greater scope of applications are subjected to differential power analysis (DPA) attacks. As a result, a good design can help maintain the confidentiality of information. Providing a design method that balances the power consumption of the outputs and inputs of chips results a DPA secure designs. Moreover, reduction of power consumption by recovering the charge stored in nodes can make the tracing power will be more difficult. On the other hand, designing a uniform pattern in the transistor surface shape for all logic gates will make them resilient against advanced imaging techniques. In this paper a DPA resilient design method is proposed which is also robust against some other attacks such as timing attacks and advanced image processing techniques. The presented designs are simulated and compared with the state of the art designs using Synopsis HSPICE with 22nm technology node. Simulation results shows that the proposed method has the lowest and most balanced power consumption compared to the other designs.