Abstract
In this paper, a linear optimization method(LOM) for the design of terahertz circuits is presented, aimed at enhancing simulation efficacy and reducing the time of the circuit design workflow. This method enables the rapid determination of optimal embedding impedance for diodes across a specific bandwidth to achieve maximum efficiency through harmonic balance simulations. By optimizing the linear matching circuit with the optimal embedding impedance, the method effectively segregates the simulation of the linear segments from the nonlinear segments in the frequency multiplier circuit, substantially increasing the speed of simulations. The design of on-chip linear matching circuits adopts a modular circuit design strategy, incorporating fixed load resistors to simplify the matching challenge. Utilizing this approach, a 340GHz frequency doubler was developed and measured. The results demonstrate that, across a bandwidth of 330GHz to 342GHz, the efficiency of the doubler remains above 10%, with an input power ranging from 98mW to 141mW and an output power exceeding 13mW. Notably, at an input power of 141mW, a peak output power of 21.8mW was achieved at 334GHz, corresponding to an efficiency of 15.8%.