High-Speed and Area Efficient Low-Power Dynamic Parity Generator and Parity Checker

Abstract

Abstract Strategic detection of an error using a parity generator and parity checker is indispensable and enforces the design engineer to optimize upscale performance. Even advanced modern communication systems can have errors due to losses/noise. This paper brings to light the design of the superior high-speed, low-power 3-bit dynamic parity generator and checker. Two, four, eight, and sixteen-bit XOR gates have been implemented using previous and proposed techniques. The proposed true single-phase dynamic XOR gate builds the parity checker and generator circuits. The proposed dynamic XOR gate, designed 3-bit parity generator, and checker circuits are compared with recently reported techniques. All circuits have been simulated using Cadence Specter on 90nm technology parameters and tested up to 1 GHz of clock frequency. Comparison is made to showcase the superiority of the proposed design in terms of power consumption, propagation delay, PDP (93.8%), EDP (98.8%), number of transistors, the figure of merit, and unity noise gain. This new 3-bit dynamic parity generator and checker would add a colossal perspective for a design engineer.