1. de Marchi, M. et al. Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs. in 2012 International Electron Devices Meeting 8.4.1–8.4.4 (IEEE, 2012).
2. Jian Zhang, Gaillardon, P.-E. & de Micheli, G. Dual-threshold-voltage configurable circuits with three-independent-gate silicon nanowire FETs. in 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013) 2111–2114 (IEEE, 2013).
3. Gaillardon, P.-E., Amaru, L., Zhang, J. & Micheli, G. de. Advanced system on a chip design based on controllable-polarity FETs. in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014 1–6 (IEEE Conference Publications, 2014).
4. Raitza, M. et al. Exploiting transistor-level reconfiguration to optimize combinational circuits. in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 338–343 (IEEE, 2017).
5. Designing efficient circuits based on runtime-reconfigurable field-effect transistors;Rai S;IEEE Trans Very Large Scale Integr VLSI Syst,2019