Inductive Line Tunneling FET Using Epitaxial Tunnel Layer with Ge-Source and Charge Enhancement Insulation

Abstract

Abstract In this paper, we propose a inductive line tunneling FET using Epitaxial Tunnel Layer with Ge-Source and Charge Enhancement Insulation (CEI ETL GS-iTFET). The CEI ETL GS-iTFET allows full overlap between the gate and source regions, thereby enhancing the line tunneling. In addition, a germanium layer is introduced on the source side to form a heterojunction, effectively improving the device's conduction current. An ETL is incorporated to combat tunneling leakage, resulting in a steeper subthreshold swing. Furthermore, a CEI consisting of Si3N4 is introduced between the germanium source and the Schottky metal, which effectively reduces carrier losses in the inversion layer and improves the overall device performance. This study presents a calibration-based approach to simulations, taking into account practical process considerations. Simulation results show that at VD = 0.2 V, the CEI ETL GS-iTFET achieves an average subthreshold swing (SSavg) of 30.5 mV/dec, an Ion of 3.12x10-5 A/μm and an Ion/Ioff ratio of 1.81x1010. These results demonstrate a significantly low subthreshold swing and a high current ratio of about 1010. In addition, the proposed device eliminates the need for multiple implantation processes, resulting in significant manufacturing cost reductions. As a result, the CEI ETL GS-iTFET shows remarkable potential in future low-power device competition.