Design of CMOS Low Noise and High Responsivity Terahertz Linear Array Detector

Abstract

This paper presents the design of a low-noise, high-responsivity terahertz linear array detector circuit based on CMOS 0.18µm technology. We propose a 1×4 terahertz detector array structure composed of a self-mixing power detection circuit, voltage buffer stage, and low-noise operational amplifier. The self-mixing power detection circuit utilizes a source-coupled differential drive approach to couple terahertz differential signals to the gate and source of the field-effect transistor, enhancing the intensity of terahertz signals within the transistor channel and achieving high responsivity. The voltage buffer stage effectively collects output signals from the detection circuit and reduces noise contributions from the main operational amplifier, thereby lowering overall noise. The low-noise operational amplifier efficiently amplifies detection signals, thereby enhancing detector responsivity. The overall area of the 1×4 detector array is 0.8mm². Test results indicate that when the gate bias of the detector core is set to 0.5V, the detector system achieves a maximum voltage responsivity (R_V) of 441 kV/W for a 0.37THz radiation signal, with a corresponding minimum noise equivalent power (NEP) of 48 pW/Hz^1/2. Compared to single-pixel detectors, this detector array effectively enhances detection imaging speed, while compared to traditional detector arrays, it exhibits superior performance parameters.