HS-HA: Design of High-Speed Hardware Accelerator SOC for Biomedical Applications-Reference-Cited by-同舟云学术

HS-HA: Design of High-Speed Hardware Accelerator SOC for Biomedical Applications

Published:2023-08-09 Issue: Volume: Page:
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Author:

Mavinkattimath Swati¹^ORCID,Khanai Rajashri¹,Torse Dattaprasad¹,Iyer Nalini²

Affiliation:

1. KLE DR MSSCET: DR MS Sheshgiri College of Engineering and Technology

2. KLE Technological University

Abstract

Abstract Wireless Body Sensor Networks (WBSNs) consists of a Microcontroller used to process biosignals from sensors connected in or on the body. However, one of the issues observed in traditional WBSN is speed, which is addressed specifically in this work. This paper explains the operation of a Hardware Accelerator (HA) for WBSN consisting of four processing techniques Register bank, Predictor, Encryption, and Error Control Coding (ECC) implemented using Field Programmable Gate Array (FPGA) board PYNQ Z2 by TUL corporation. The improvements in the design of WBSN using HA are observed through the results of synthesis and implementation. The values of Worst Negative Slack (WNS) and utilization report represents the improvements in the design. HA’s floor planning and routing during Hardware-Software co-design produced a WNS of 0.269 ns. The proposed HA design in this paper utilizes 5.69k gate counts and consumes 0.227mW of power when operating at 250 MHz by using a 28-nm CMOS process.

Publisher

Research Square Platform LLC

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