Reconfigurable Two-dimensional Floating Gate Field-effect Transistors for Highly Integrated In-memory Computing

Abstract

Abstract With the increasing need for highly integrable and energy-efficient hardware for cutting-edge applications, such as neuromorphic and in-memory computing, reconfigurable devices with multi-functional operations are essential for these applications, enhancing performance and area efficiency. However, traditional reconfigurable devices suffer from limited functionality and circuit incompatibility due to the adoption of multiple gates, leading to increased system complexity and manufacturing costs. This work demonstrates reconfigurable floating-gate field-effect transistors (R-FGFETs) based on van der Waals (vdW) heterostructure to implement highly integrable and reconfigurable circuits for in-memory computing with minimum overhead. By modulating the charge trapping within the graphene floating gate using a single gate terminal, R-FGFETs can attain four distinct electrical conducting states: metallic, n- and p-type semiconducting, and insulating. By incorporating these R-FGFETs into reconfigurable combinatorial computing units, programmable logic and arithmetic operations, including 16 Boolean logic gates, addition, subtraction, and comparison, are feasibly achieved with minimal overhead. Also, a novel method is proposed to address voltage mismatch between input and output through programming voltage-dependent threshold voltage shift, facilitating efficient connections between logic gates. This work offers a potential pathway for highly integrating a reconfigurable processor based on vdW heterostructures, thus providing an area- and energy-efficient solution.