Flexible and Parallel Architectures for Optimal Ate pairing on FPGA

Abstract

Abstract This paper presents three approaches for the implementation of Optimal Ate pairing based on Jacobean coordinates, over Barreto-Naehrig curves, targeting the 128 bits security level, in Genesys board. The first approach is a fully software implementation using MicroBlaze processor. The second approach is software/hardware implementation, in which the most useful operations in \({\varvec{F}}_{\varvec{p}}\) and \({\varvec{F}}_{{\varvec{p}}^{2}}\) are coded as intellectual property cores around the Microblaze. The third approach is based on the second in which we exploit the parallelism that exists to compute Optimal Ate pairing. The integration of multi-MicroBlaze processor in single architecture allows not only the flexibility of the overall system but also the parallelism to speed up pairing. Various techniques and parameters are used and combined to compute Optimal Ate in efficient way, namely: Montgomery modular multiplication, Karatsuba method, Jacobean coordinate, Complex method for squaring, Sparse multiplication, squaring in the cyclotomic subgroup \({\varvec{G}}_{\varvec{\varphi }6}\left({\varvec{F}}_{{\varvec{p}}^{12}}\right)\) and addition chain method. Our flexible and parallel systems are dedicated for restricted environment resources with a reasonable execution time.