High-speed binary coded decimal digit multipliers with multiple error detection

Abstract

Abstract Decimal arithmetic in the form of binary coded decimal (BCD) numbers is preferred in many financial and commercial applications. BCD multipliers are introduced as a key hardware unit to support both integer and floating-point decimal arithmetic operations. However, due to the increasing sensitivity of VLSI-based digital designs to the environmental effects, BCD multipliers are also prone to faults and errors similar to other arithmetic circuits. In addition, multiple error occurrence is possible in current digital systems which motivates to reach multiple error detection/correction in addition to single errors. In this paper, digit-by-digit BCD multipliers are introduced capable of multiple error detection with low delay overheads. To show the effectiveness of the proposed combined method, a 4-digit BCD multiplier is presented. Experimental results based on analysis and error injection-based simulations show that in addition to 100% single error detection, multiple errors can be detected with at least 99.6% probability in the 4-digit BCD multiplier as the implemented architecture.