The assessment of Noise Immunity in Domino Employing Silicon Nano Materials

Abstract

Abstract This article describes a novel Low Voltage Noise Immune Domino Logic (LVNIDL), which can be used to create CMOS domino using Si Nanomaterials. In 32 nm nano size silicon CMOS technology, wide fan-in input domino OR gate have been proposed and have already undergone HSPICE simulation. For the transient analysis of domino gates in the simulation, a D.C supply voltage of 0.9V and a frequency of 100 MHz are utilised. The proposed technique consumes 76.07% less power than the preceding conditional stacked keeper domino logic. Furthermore, when compared to the existing CPVT technique, the designed LVNIDL technique reduces maximum delay by 56.25%. The LVNIDL technique boosts the power delay product by up to 88.54% and the EDP by up to 95.31% when compared to earlier domino. In terms of unity noise gain, the LVNIDL technique outperforms the earlier domino by 1.09 to 1.47 times.