Network-on-chip router input port architectures

Abstract

Abstract With the increase in the number of processing cores on a chip, a highly efficient and scalable structure such as a network on a chip was proposed. Network-on-chip is a technology presented to solve the limitations of system-on-chip that includes a set of multiprocessors. In network-on-chip systems, delay in communication and reaching the ideal speed is one of the concerns of academic and industrial researchers today. Although network-on-chip offers a favorable solution to reduce the problem of the long delay of wires compared to traditional structures, communication delay is still a challenge. In this article, the various types of network router input ports architecture on the chip are reviewed and the operational comparison and evaluation of the technologies proposed in this field are mentioned.