Design of All Digital Phase Locked Loop with Digitally Controlled Oscillator Using 45nm for Low Power Consumption

Abstract

Abstract A low-power consuming device All Digital Phase Locked Loop (ADPLL) has grown more appealing due to improved verifiability, flexibility, reliability, and portability over various processes as well as improved noise resistance. ADPLL is a negative feedback system that creates a high-frequency clock signal in the phase relationship to a low-frequency reference signal. In this proposed work, an ADPLL was developed using 45 nm CMOS technology with a Digital Control Oscillator (DCO) to fulfill the requirements of system implementation because the DCO can attain both better resolution and a large bandwidth spectrum. The Cadence Virtuoso software is employed for verification and simulation to affirm its features and functions. Control bits created by the Digital Loop Filter (DLF) are utilized to electronically regulate the DCO output frequency range. The loop is deemed to be held at 12ns once the reference signal and divided output clock frequency have been associated. The simulation results showed that the designed ADPLL achieves a (peak-to-peak) p2p jitter of 60 ps between 880 MHz − 1 GHz and a root means square (RMS) value of 1ps. The layout area estimated is 1.188 mm2. The DCO consumes 288 \(\mu\)W and the overall energy consumption is 2.66 mW with a power source of 1.2 V.