A PAM4 transceiver design scheme with threshold adaptive and tap adaptive

Abstract

Abstract To meet the demand of low bit error rate (BER) and high bandwidth for high-speed links, a reliable 112Gb/s four-level pulse amplitude modulation (PAM4) transceiver design scheme with adaptive threshold voltage and adaptive decision feedback equalizer (DFE) is proposed in this paper. In this scheme, three continuous time linear equalizers (CTLE) at the front end of receiver are used to compensate the high-frequency, mid-frequency and low-frequency signals respectively, and the variable gain amplifier (VGA) and saturation amplifier (SatAmp) are used to scale the signal amplitude. In addition to the three data samplers, four auxiliary samplers are also used for threshold adaptation. The sign-sign least mean squares algorithm uses the offset between the data sampler and the auxiliary sampler at the receiver side to drive the auxiliary reference voltage to converge to the signal constellation level, thus ensuring that the eye diagram of the PAM4 received signal has equal spacing and a constant signal-noise ratio (SNR) for the three eyes in the vertical direction. In addition, the adaptive DFE for PAM4 signaling allows the transceiver to better adapt to the channel and thus achieve better equalizer performance. The simulation results show that the PAM4 transceiver design can compensate up to 25dB of channel loss with an average eye height of 59.6 mv and an average eye width of 0.27 UI at a bit error rate of 10− 12 under the condition of 3 tap Feedforward equalizer (FFE) transmitter.