1. [1] Liu, C.P.L. and Abraham, J.A.: Transistor Level Synthesis for Static CMOS Combinational Circuits, Great Lakes Symposium on VLSI, pp.172-175 (1999).
2. [2] Kagaris, D. and Haniotakis, T.: Transistor-Level Synthesis for Low-Power Applications, International Symposium on Quality Electronic Design, pp.607-612 (2007).
3. [3] Burns, J.L. and Feldman, J.A.: C5M-a control-logic layout synthesis system for high-performance microprocessors, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol.17, No.1, pp.14-23 (1998).
4. [4] Onodera, H., Hashimoto, M. and Hashimoto, T.: ASIC design methodology with on-demand library generation, Symposium on VLSI Circuits, pp.57-60, Japan Soc. Appl. Phys. (2001).
5. [5] Hashimoto, M., Fujimori, K. and Onodera, H.: Automatic Generation of Standard Cell Library in VDSM Technologies 2 Layout generation system: VARDS, International Symposium on Quality Electronic Design, pp.36-41 (2004).