1. 1) Calypto's SLEC System. www.calypto.com/slecsystem.php
2. 2) Esterel's SCADE Design Verifier. www.esterel-technologies.com/products/scade-suite/design-verifier
3. 3) Microsoft's Static Driver Verifier (SDV). www.microsoft.com/whdc/devtools/tools/SDV.mspx
4. 4) Telelogic's Statemate. modeling.telelogic.com/products/statemate/index.cfm
5. 5) Ashar, P., Bhattacharya, S., Raghunathan, A. and Mukaiyama, A.: Verification of RTL generated from scheduled behavior in a high-level synthesis flow, ICCAD, pp.517-524 (1998).