Parallelizing Random and SAT-based Verification Processes for Improving Toggle Coverage
Author:
Affiliation:
1. Department of Information and Computer Science, Faculty of Engineering, Kyoto Tachibana University
Publisher
Information Processing Society of Japan
Subject
Electrical and Electronic Engineering,Computer Science Applications
Link
https://www.jstage.jst.go.jp/article/ipsjtsldm/16/0/16_45/_pdf
Reference19 articles.
1. [1] Kakiuchi, Y. and Hamaguchi, K.: Coverage-driven Design Verification Using a Diverse SAT Solver, IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, Vol.E100-A, No.7, pp.1481-1487 (2017).
2. [2] Hamaguchi, K.: Applying an SMT Solver to Coverage-Driven Design Verification, IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, Vol.E101-A, No.7, pp.1053-1056 (2018).
3. [3] Yang, S., Wille, R., Große, D. and Drechsler, R.: Coverage-driven stimuli generation, EUROMICRO Symp. Digital System Design, pp.525-528 (2012).
4. [4] Yang, S., Wille, R. and Drechsler, R.: Determining cases of scenarios to improve coverage in simulation-based verification, Symp. Integrated Circuits and System Design (2014).
5. [5] Wagner, I., Bertacco, V. and Austin, T.: Microprocessor Verification via Feedback-Adjusted Markov Models, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol.26, No.6, pp.1126-1138 (2007).
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