1. [1] Miura, N., Take, Y., Saito, M., Yoshida, Y. and Kuroda, T.: A 2.7Gb/s/mm2 0.9pJ/b/chip 1coil/channel ThruChip interface with coupled-resonator-based CDR for NAND Flash memory stacking, IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp.490-492 (2011).
2. [2] Dorsey, P.: Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity, Bandwidth, and Power Efficiency, Xilinx white paper (2010).
3. [3] Maly, W.P. and Yangdong, D.: 2.5-dimensional VLSI system integration, IEEE Trans. Very Large Scale Integration (VLSI) System, pp.668-677 (2005).
4. [4] Yu, C.H.: The 3rd dimension-More Life for Moore's Law, Microsystems, Packaging, Assembly Conference, pp.1-6 (2006).
5. [5] Kim, J.S. et al.: A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128I/Os using TSV-based stacking, IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp.496-498 (2011).