1. [1] Xilinx Vitis High-Level Synthesis, available from <https://www.xilinx.com/products/design-tools/vivado/integration/esl-design.html>.
2. [2] Intel High Level Synthesis Compiler, available from <https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/hls-compiler.html>.
3. [3] Canis, A., Choi, J., Fort, B., Lian, R., Huang, Q., Calagar, N., Gort, M., Qin, J.J., Aldham, M., Czajkowski, T., et al.: From software to accelerators with LegUp high-level synthesis, 2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), pp.1-9, IEEE (2013).
4. [4] Settle, S.O. et al.: High-performance dynamic programming on fpgas with opencl, Proc. IEEE High Perform. Extreme Comput. Conf. (HPEC), pp.1-6 (2013).
5. [5] Vesper, M., Kocha, D. and Phama, K.: PCIeHLS: An OpenCL HLS framework, FSP 2017; 4th International Workshop on FPGAs for Software Programmers, VDE, pp.1-6 (2017).