From Process Variations to Reliability: A Survey of Timing of Digital Circuits in the Nanometer Era-Reference-Cited by-同舟云学术

From Process Variations to Reliability: A Survey of Timing of Digital Circuits in the Nanometer Era

Published:2018 Issue:0 Volume:11 Page:2-15
ISSN:1882-6687
Container-title:IPSJ Transactions on System LSI Design Methodology
language:en
Short-container-title:IPSJ Transactions on System LSI Design Methodology

Author:

Li Bing¹,Hashimoto Masanori²,Schlichtmann Ulf¹

Affiliation:

1. Technical University of Munich

2. Osaka University

Publisher

Information Processing Society of Japan

Subject

Electrical and Electronic Engineering,Computer Science Applications

Link

https://www.jstage.jst.go.jp/article/ipsjtsldm/11/0/11_2/_pdf

Reference101 articles.

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2. [2] Nassif, S.R.: Modeling and Analysis of Manufacturing Variations, Proc. Custom Integr. Circuits Conf. (CICC), pp.223-228 (2001).

3. [3] Blaauw, D., Chopra, K., Srivastava, A. and Scheffer, L.: Statistical Timing Analysis: From Basic Principles to State of the Art, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., Vol.27, No.4, pp.589-607 (2008).

4. [4] Dennard, R.H., Gaensslen, F.H., Yu, H.-N., Rideout, V.L., Bassous, E. and Leblanc, A.R.: Design of ion-implanted MOSFETs with very small physical dimensions, IEEE J. Solid-State Circuits, Vol.9, No.5, pp.256-268 (1974).

5. [5] Yang, J., Capodieci, L. and Sylvester, D.: Advanced timing analysis based on post-OPC extraction of critical dimensions, Proc. Design Autom. Conf. (DAC), pp.359-364 (2005).

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