Framework for Latch-based High-level Synthesis Using Minimum-delay Compensation

Author:

Inoue Keisuke,Kaneko Mineo

Publisher

Information Processing Society of Japan

Subject

Electrical and Electronic Engineering,Computer Science Applications

Reference13 articles.

1. 1) Inoue, K. and Kaneko, M.: Optimal register assignment with minimum-delay compensation for latch-based design, Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) (Dec. 2010).

2. 2) Chinnery, D., Nikolic, B. and Keutzer, K.: Achieving 550MHz in an ASIC methodology, Proc. IEEE Design Automation Conference (DAC), pp.420-425 (2001).

3. 3) Yang, W., Park, I.-C. and Kyung, C.-M.: Low-power high-level synthesis using latches, Proc. IEEE Asia South Pacific Design Automation Conference (ASP-DAC), pp.462-466 (Jan. 2001).

4. 4) Wu, T. and Lin, Y.: Storage optimization by replacing some flip-flops with latches, Proc. IEEE Euro-DAC, pp.296-301 (Sep. 1996).

5. 5) Chen, Y. and Xie, Y.: Tolerating process variations in high-level synthesis using transparent latches, Proc. IEEE ASP-DAC, pp.73-78 (Jan. 2009).

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