1. [1] PTM, available from <http://ptm.asu.edu/>.
2. [2] Aho, A.V., Sethi, R. and Ullman, J.D.: Compilers: Principles, Techniques, and Tools, Addison-Wesley Publishing Company, Reading, Massachusetts (1986).
3. [3] Breach, S.E., Vijaykumar, T.N. and Sohi, G.S.: The Anatomy of the Register File in a Multiscalar Processor, Proc. 27th International Symposium on Microarchitecture, pp.181-190 (1994).
4. [4] Campanoni, S., Brownell, K., Kanev, S., Jones, T.M., Wei, G.-Y. and Brooks, D.: HELIX-RC: An architecture-compiler co-design for automatic parallelization of irregular programs, Proc. 41st Annual International Symposium on Computer Architecuture, pp.217-228 (2014).
5. [5] Hamerly, G., Perelman, E., Lau, J. and Calder, B.: SimPoint 3.0: Faster and more flexible program analysis, Journal of Instruction-Level Parallelism, Vol.7, pp.1-28 (2005).