Affiliation:
1. Department of ECE, Koneru Lakshmaiah Education Foundation, Vaddeswaram, India
Abstract
In this paper, the design and simulation of a high-speed, low power 6-T
XOR-XNOR circuit is carried out. Also, the design and simulation of 1-bit
hybrid full adder (consisting of 16 transistors) using XOR-XNOR circuit,
sum, and carry, is performed to improve the area and speed performance. Its
performance is being compared with full adder designs with 20 and 18
transistors, respectively. The performance of the proposed circuits is
measured by simulating them in Microwind tool using 180 and 90nm CMOS
technology. The performance of the proposed circuit is measured in terms of
power, delay, and PDP (Power Delay Product).
Publisher
National Library of Serbia
Subject
General Materials Science