Design guidelines to achieve minimum energy operation for ultra low voltage tunneling FET logic circuits

Author:

Fuketa Hiroshi,Yoshioka Kazuaki,Fukuda Koichi,Mori Takahiro,Ota Hiroyuki,Takamiya Makoto,Sakurai Takayasu

Publisher

IOP Publishing

Subject

General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering

Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Semiconductor-Thickness-Dependent Design of Hetero-Gate Dielectric in Double-Gate TFETs;2020 IEEE Eighth International Conference on Communications and Electronics (ICCE);2021-01-13

2. Minimum-Energy Digital Computing With Steep Subthreshold Swing Tunnel FETs;IEEE Journal on Exploratory Solid-State Computational Devices and Circuits;2020-12

3. DC and analog/RF performance analysis of gate extended U-shaped channel tunnel field effect transistor;Microsystem Technologies;2020-04-15

4. A perspective on steep-subthreshold-slope negative-capacitance field-effect transistor;Applied Physics Express;2018-10-22

5. A Closed-Form Expression for Minimum Operating Voltage of CMOS D Flip-Flop;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2017-07

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