Low-frequency noise reduction in vertical MOSFETs having tunable threshold voltage fabricated with 60 nm CMOS technology on 300 mm wafer process
Author:
Publisher
IOP Publishing
Subject
General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering
Link
http://stacks.iop.org/1347-4065/54/i=4S/a=04DC11/pdf
Reference44 articles.
1. Simulation of Statistical Variability in Nano MOSFETs
2. Analysis of NMOS and PMOS Difference in $V_{T}$ Variation With Large-Scale DMA-TEG
3. Quantitative Evaluation of Statistical Variability Sources in a 45-nm Technological Node LP N-MOSFET
4. Empirical Characteristics and Extraction of Overall Variations for 65-nm MOSFETs and Beyond
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