Radiation hardness evaluations of 65 nm fully depleted silicon on insulator and bulk processes by measuring single event transient pulse widths and single event upset rates
Author:
Publisher
IOP Publishing
Subject
General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering
Link
http://stacks.iop.org/1347-4065/54/i=4S/a=04DC15/pdf
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1. Single Event Upset Evaluation for a 28-nm FDSOI SRAM Type Buffer in an ARM Processor;Journal of Electronic Testing;2021-03-31
2. Evaluation of Soft-Error Tolerance by Neutrons and Heavy Ions on Flip Flops With Guard Gates in a 65-nm Thin BOX FDSOI Process;IEEE Transactions on Nuclear Science;2020-07
3. Radiation-Hardened Structure to Reduce Sensitive Range of a Stacked Structure for FDSOI;IEEE Transactions on Nuclear Science;2019-07
4. Analyzing Impacts of SRAM, FF and Combinational Circuit on Chip-Level Neutron-Induced Soft Error Rate;IEICE Transactions on Electronics;2019-04-01
5. The Impact of Charge Collection Volume and Parasitic Capacitance on SEUs in SOI- and Bulk-FinFET D Flip-Flops;IEEE Transactions on Nuclear Science;2018-01
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