Compact 0.3-to-1.125 GHz self-biased phase-locked loop for system-on-chip clock generation in 0.18 µm CMOS
Author:
Publisher
IOP Publishing
Subject
General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering
Link
http://stacks.iop.org/1347-4065/55/i=4S/a=04EF05/pdf
Reference32 articles.
1. A 7.1 mW, 10 GHz All Digital Frequency Synthesizer With Dynamically Reconfigured Digital Loop Filter in 90 nm CMOS Technology
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3. A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Self-Biased PLL-Based Multiphase Clock Generator;IEEE Journal of Solid-State Circuits;2020-10
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5. A 0.9–2.25-GHz Sub-0.2-mW/GHz Compact Low-Voltage Low-Power Hybrid Digital PLL With Loop Bandwidth-Tracking Technique;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2018-05
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