Scaling limit for InGaAs/GaAsSb heterojunction double-gate tunnel FETs from the viewpoint of direct band-to-band tunneling from source to drain induced off-characteristics deterioration-Reference-Cited by-同舟云学术

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Scaling limit for InGaAs/GaAsSb heterojunction double-gate tunnel FETs from the viewpoint of direct band-to-band tunneling from source to drain induced off-characteristics deterioration

Published:2016-06-21 Issue:7 Volume:55 Page:070303
ISSN:0021-4922
Container-title:Japanese Journal of Applied Physics
language:
Short-container-title:Jpn. J. Appl. Phys.

Author:

Lin Wenbo,Iwata Shinjiro,Fukuda Koichi,Miyamoto Yasuyuki

Publisher

IOP Publishing

Subject

General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering

Link

http://stacks.iop.org/1347-4065/55/i=7/a=070303/pdf

Reference22 articles.

1. Low-Voltage Tunnel Transistors for Beyond CMOS Logic

2. Tunnel field-effect transistors as energy-efficient electronic switches

3. Double-Gate Tunnel FET With High-$\kappa$ Gate Dielectric

4. Steep Subthreshold Slope n- and p-Type Tunnel-FET Devices for Low-Power and Energy-Efficient Digital Circuits

5. Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Circuit speed oriented device design scheme for GaAsSb/InGaAs double-gate hetero-junction tunnel FETs;Japanese Journal of Applied Physics;2020-02-04

2. Simulation study of short-channel effects of tunnel field-effect transistors;Japanese Journal of Applied Physics;2018-02-26

3. InAs/InGaAsSb/GaSb Nanowire Tunnel Field-Effect Transistors;IEEE Transactions on Electron Devices;2017-11

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