Physical modeling of program and erase speeds of metal–oxide–nitride–oxide–silicon cells with three-dimensional gate-all-around architecture-Reference-Cited by-同舟云学术

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Physical modeling of program and erase speeds of metal–oxide–nitride–oxide–silicon cells with three-dimensional gate-all-around architecture

Published:2013-12-20 Issue:1 Volume:53 Page:014201
ISSN:0021-4922
Container-title:Japanese Journal of Applied Physics
language:
Short-container-title:Jpn. J. Appl. Phys.

Author:

Lee Gae-Hun,Yang Hyung-Jun,Jung Sung-Wook,Choi Eun-Seok,Park Sung-Kye,Song Yun-Heub

Publisher

IOP Publishing

Subject

General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering

Reference24 articles.

1. Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory

2. Novel 3-D structure for ultra high density flash memory with VRAT (Vertical-Recess-Array-Transistor) and PIPE (Planarized Integration on the same PlanE)

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. High-density 3D-NAND flash with dual-string select line (D-SSL);Engineering Research Express;2024-08-20

2. Concave and Convex Structures for Advanced 3-D NAND Flash Memory Technology;IEEE Transactions on Electron Devices;2024-04

3. Impact of P/E Stress on Trap Profiles in Bandgap-Engineered Tunneling Oxide of 3D NAND Flash Memory;IEEE Access;2022

4. A Novel Program Operation Scheme With Negative Bias in 3-D NAND Flash Memory;IEEE Transactions on Electron Devices;2021-12

5. Overcoming bit loss mechanism in self‐amplified multilevel silicon‐oxide‐nitride‐oxide‐silicon memory cell;International Journal of Numerical Modelling: Electronic Networks, Devices and Fields;2021-06-22

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