Design of a highly reliable, high-speed MTJ-based lookup table circuit using fractured logic-in-memory structure-Reference-Cited by-同舟云学术

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Design of a highly reliable, high-speed MTJ-based lookup table circuit using fractured logic-in-memory structure

Published:2019-02-25 Issue:SB Volume:58 Page:SBBB10
ISSN:0021-4922
Container-title:Japanese Journal of Applied Physics
language:
Short-container-title:Jpn. J. Appl. Phys.

Author:

Suzuki Daisuke,Hanyu Takahiro

Publisher

IOP Publishing

Subject

General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering

Link

http://stacks.iop.org/1347-4065/58/i=SB/a=SBBB10/pdf

Reference31 articles.

1. Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Reliability-Enhanced Differential Sensing Amplifier for Hybrid CMOS/MTJ Logic Circuits;Electronics;2023-01-15

2. MESO-LUT: A design approach of look up tables based on MESO devices;Microelectronics Journal;2022-08

3. Nonvolatile Field-Programmable Gate Array Using a Standard-Cell-Based Design Flow;IEICE Transactions on Information and Systems;2021-08-01

4. Design of an energy-efficient binarized convolutional neural network accelerator using a nonvolatile field-programmable gate array with only-once-write shifting;Japanese Journal of Applied Physics;2021-03-25

5. Design of a cost-efficient controller for realizing a data-shift-minimized nonvolatile field-programmable gate array;Japanese Journal of Applied Physics;2020-02-28

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