Reduction of process temperature for Si surface flattening utilizing Ar/H2 ambient annealing and its application to SOI-MISFETs with bilayer HfN high-k gate insulator
Author:
Publisher
IOP Publishing
Subject
General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering
Link
http://iopscience.iop.org/article/10.7567/1347-4065/ab5173/pdf
Reference38 articles.
1. Design Optimization and Modeling of Charge Trap Transistors (CTTs) in 14 nm FinFET Technologies
2. Performance Improvement by Cold Xe Pre-Amorphization Implant for Nickel Silicidation of 28-nm PMOSFET
3. Characterization and Modeling of Flicker Noise in FinFETs at Advanced Technology Node
Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. The Effect of Si Surface Flattening Process on the MISFET With High-k HfNx Multilayer Gate Dielectrics;IEEE Transactions on Semiconductor Manufacturing;2021-08
2. Ferroelectric Hafnium Nitride Thin Films Directly Formed on Si(100) Substrate;IEEE Journal of the Electron Devices Society;2021
3. Investigation of high-k HfN multilayer gate dielectrics for MISFET fabricated with Si surface flattening;2020 International Symposium on Semiconductor Manufacturing (ISSM);2020-12-15
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