Addressing Raveling Resistance in Chip Seal Specifications

Abstract

Chip seals are applied to existing roadways to slow deterioration and improve pavement surface conditions without increasing the pavement’s structural capacity. The raveling of chip seals can cause damage to vehicles and thus is a safety concern. Raveling resistance is related to both material application rates and material properties. The current chip seal specifications fail to adequately address the material-related aspects of raveling resistance. This study seeks to develop recommendations to address raveling resistance in future chip seal specifications. Strain sweep binder tests, binder bond strength (BBS) tests, and Vialit chip seal mixture tests were conducted to assess early raveling, late raveling, and wet raveling at two intermediate temperatures. The results demonstrate that the bond that develops between the residual binder and the aggregate is highly dependent on the interaction between the emulsion and the aggregate during curing. The importance of emulsion–aggregate compatibility in raveling resistance indicates that raveling resistance cannot be addressed in binder specifications alone. Rather, it is recommended that intermediate temperature raveling resistance should be addressed during chip seal mixture design. Vialit and BBS tests, in which emulsion is cured on rock, can both be used to effectively quantify the aggregate loss potential of a chip seal. These two tests are able to capture the benefits of polymer modification and produce results that correlate. However, the Vialit tests are easier to implement than the BBS tests and require no expensive equipment. Therefore, Vialit tests are recommended to address early, late, and wet raveling resistance in future chip seal specifications.