1. 2009 ISPSD K. Nakamura D. Oya S. Saito Impact of an LPT(II) concept with thin wafer process technology for IGBT's vertical structure 295 298
2. 2001 36th IAS Annual Meeting Y. Tomomatsu S. Kusunoki K. Satoh Characteristics of a 1200 V CSTBT optimized for industrial applications 1060 1065
3. 1996 ISPSD'96 Proc. IEEE H. Takahashi E. Haruguchi H. Hagino Carrier stored trench‐gate bipolar transistor (CSTBT) – a novel power device for high voltage application 349 352
4. 2010 ISPSD 2010 K. Nakamura K. Sadamatsu D. Oya Wide cell pitch LPT(II)‐CSTBT(III) technology rating up to 6500 V for low loss 387 390
5. 2006 ISPSD'06 K. Nakamura Y. Hisamoto T. Matsumura The second stage of a thin wafer IGBT low loss 1200 V LPT‐CSTBT with a backside doping optimization process