Efficient layout design automation for multi‐chip SiC modules targeting small footprint and low parasitic-Reference-Cited by-同舟云学术

Efficient layout design automation for multi‐chip SiC modules targeting small footprint and low parasitic

Published:2020-08 Issue:10 Volume:13 Page:2069-2076
ISSN:1755-4543
Container-title:IET Power Electronics
language:en
Short-container-title:IET Power Electronics

Author:

Mei Yunhui¹²^ORCID,Hao Baisen¹²,Chen Yue¹²,Wang Meiyu¹²,Li Xin¹²,Lu Guo‐Quan³⁴

Affiliation:

1. Key Laboratory of Advanced Ceramics and Machining Technology of Ministry of EducationTianjin UniversityTianjin300350People's Republic of China

2. School of Materials Science and EngineeringTianjin UniversityTianjin300350People's Republic of China

3. Department of Materials Science and EngineeringVirginia TechBlacksburgVA24061USA

4. Bradley Department of Electrical and Computer EngineeringVirginia TechBlacksburgVA24061USA

Funder

National Natural Science Foundation of China

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-pel.2019.1345

Reference37 articles.

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2. Temperature and switching rate dependence of crosstalk in Si‐IGBT and SiC power modules;Jahdi S.;IEEE Trans. Ind. Electron.,2017

3. Parasitic inductance and capacitance assisted active gate driving technique to minimize switching loss of SiC MOSFET;Nayak P.;IEEE Trans. Ind. Electron.,2017

4. Reliability evaluation of multichip phase‐leg IGBT modules using pressureless sintering of nanosilver paste by power cycling tests;Fu S.;IEEE Trans. Power Electron.,2017

5. 2011 Proc. 26 Applied Power Electronics Conf. Exposition Fort Worth TX USA S. Li L.M. Tolbert F. Wang P‐cell and N‐cell based IGBT module: layout design parasitic extraction and experimental verification 372 378

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