An analog‐to‐digital converter calibration algorithm with clock jitter compensation based on bidirectional long‐short‐time‐memory-Reference-Cited by-同舟云学术

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An analog‐to‐digital converter calibration algorithm with clock jitter compensation based on bidirectional long‐short‐time‐memory

Published:2022-08-11 Issue:20 Volume:58 Page:753-755
ISSN:0013-5194
Container-title:Electronics Letters
language:en
Short-container-title:Electronics Letters

Author:

Zeng Jialong¹²,Wan Jiangpeng³,Chen Dongxu¹,Yang Xudong¹,Yu Zhongjun¹²

Affiliation:

1. Aerospace Information Research Institute Chinese Academy of Sciences Beijing China

2. School of Electronic, Electrical and Communication Engineering University of Chinese Academy of Sciences Beijing China

3. Beijing Jiaotong University Beijing China

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/ell2.12598

Reference12 articles.

1. Digitally Calibrated 768-kS/s 10-b Minimum-Size SAR ADC Array With Dithering

2. A 46 $\mu \text{W}$ 13 b 6.4 MS/s SAR ADC With Background Mismatch and Offset Calibration

3. Background Digital Calibration of Comparator Offsets in Pipeline ADCs

4. Neural-Network Based Self-Initializing Algorithm for Multi-Parameter Optimization of High-Speed ADCs

5. Zhang T.et al.:Machine learning based prior‐knowledge‐free calibration for split pipelined‐SAR ADCs with open‐loop amplifiers achieving 93.7‐dB SFDR. In:IEEE European Solid State Circuits Conference (ESSCIRC) pp.189–192(2019).

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1. Genetic neural network based background calibration method for pipeline ADC;Microelectronics Journal;2024-09

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