Suppressed threshold voltage roll-off characteristic of 40 nm gate length ultrathin SOI MOSFET
Author:
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://digital-library.theiet.org/content/journals/10.1049/el_19981433?crawler=true&mimetype=application/pdf
Reference8 articles.
1. Scaling the Si MOSFET: from bulk to SOI to bulk
2. Monte Carlo simulation of a 30 nm dual-gate MOSFET: how short can Si go?
3. Sub-50 nm gate length n-MOSFETs with 10 nm phosphorus source and drain junctions
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1. The end of CMOS scaling;IEEE Circuits and Devices Magazine;2005-01
2. Systematic electrical characteristics of ideal rectangular cross section si-fin channel double-gate MOSFETs fabricated by a wet process;IEEE Transactions On Nanotechnology;2003-12
3. Fin-Type Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistors Fabricated by Orientation-Dependent Etching and Electron Beam Lithography;Japanese Journal of Applied Physics;2003-06-30
4. New silicon devices beyond CMOS;Journal de Physique IV (Proceedings);2002-05
5. Technology for the fabrication of ultrashort channel metal–oxide–semiconductor field-effect transistors;Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films;2001-07
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