Modified maximum a posteriori decoder architecture for low‐power consumption-Reference-Cited by-同舟云学术

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Modified maximum a posteriori decoder architecture for low‐power consumption

Published:2013-09 Issue:7 Volume:7 Page:542-548
ISSN:1751-9675
Container-title:IET Signal Processing
language:en
Short-container-title:IET signal process.

Author:

Subramani Shiyamala¹,Vayanaperumal Rajamani²

Affiliation:

1. Department of Electronics and Communication EngineeringSri Subramanya College of Engineering and TechnologyPalaniTamilnaduIndia

2. Department of Electronics and Communication EngineeringIndra Ganesan College of EngineeringTiruchirappalliTamilnaduIndia

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Signal Processing

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-spr.2012.0271

Reference35 articles.

1. Bahl L.R. Cocke J. Jelinek F. Raviv J.: ‘Optimal decoding of linear codes for minimizing symbol error rates’.IEEE Trans. Inf. Theory 1974 20 (2) pp.284–287

2. A 140‐Mb/s, 32‐state. Radix4 Viterbi decoder;Black P.J.;Proc. IEEE J. Solid‐State Circuits,1992

3. Berrou C. Glavieux A. Thitimajshima P.: ‘Near Shannon limit error‐correcting coding and decoding: turbo codes (1)’.Proc. IEEE Int. Conf. on Communications (ICC) 1993 pp.1064–1070

4. Garret D. Stan M.: ‘Low power architecture of the soft‐output Viterbi algorithm’.Proc. Int. Symp. on Low Power Electronics and Design (ISLPED) 1998 pp.262–267

5. Power management in high‐level synthesis;Lakshminarayana G.;IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,1999

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